Communication between components on a host platform is necessary for operation of an electronic device. However, various conditions affect the timing of high-speed communication between components, such as temperature change and voltage variation. In general, the communication among different components can be referred to as I/O (input/output), and is frequently governed by standards (e.g., between components of a memory subsystem). The I/O standards can relate to performance characteristics for I/O power, I/O latency, and I/O frequency. The standards or nominal values of I/O performance settings are set to values that can be achieved across different systems for compatibility and interoperability. Typically, there are tradeoffs between power and latency. Thus, using tight timing parameters can reduce power, but causes the I/O latency to be more negatively affected by temperature, voltage, and process variation.
In memory subsystems, it is common to use a matched architecture, where both a data path (DQ) and a data strobe path (DQS) are amplified by matched continuous time amplifiers. FIG. 1A is a block diagram of a known matched receiver circuit. In matched architecture 102, amplifier 122 of the data path is matched to both amplifier 124 and clock distribution network 130 of the strobe path. The data path includes data input DQ[7:0] input into amplifier 122 with internal Vref signal 110. The data strobe path includes inputs for a strobe for p-type devices (DQS_P) and for a strobe for n-type devices (DQS_N). Amplifier 124 feeds into clock distribution network 130, which provides a network to distribute the clock signal to multiple recipient devices at the same time. Specifically shown is a signal going to elements 142 and 144 of sampling circuit 140.
Using an unmatched architecture can improve the receiver's power and performance as compared to using a matched architecture. FIG. 1B is a block diagram of a known unmatched receiver circuit. In unmatched architecture 104, the data (DQ) voltage is sampled directly at the pad. After being sampled, the system can amplify the signal without the tight timing constraints needed for matched architecture 102. Namely, amplification can occur over an entire UI (unit interval) or possibly more. Thus, the gain/bandwidth requirements of the unmatched receiver are lower than that of the matched receiver. As illustrated, DQ[7:0] and internal Vref 110 are fed directly to elements 162 and 164 of sampling circuit 160. The DQS path still requires a continuous time amplifier, amplifier 126, but the swing on DQS is typically larger than the swing on DQ, which means a lower gain amplifier 126 can be used, as it does not have to be matched to a high gain amplifier in the data path.
Unmatched architecture 104 improves certain receiver bandwidth and voltage sensitivities with respect to matched architecture 102, but degrades the timing control. The delay on the DQS and DQ paths are not self-compensating in unmatched architecture 104. Thus, any change in TDQS, or the time to propagate a strobe signal through clock distribution network 130, will directly degrade the receiver timing budget. Existing training can correct the timing once, but any drift from the trained position will directly affect timing margin. Drift can occur across voltage, temperature, and/or aging, which will degrade timing margins and possibly create link failures.
Periodic training is known in which training data is written across the link (e.g., from a memory controller to a DRAM (dynamic random access memory)) and checked for errors. However, periodic training suffers from complexity and load on the bus bandwidth. Additionally, the training would be most effective if a large number of samples were averaged, but averaging more samples directly conflicts with performance requirements and feedback loop bandwidth. Furthermore, known periodic training is inherently slow because of the iterative nature of the feedback loop of existing training methods.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.